The present invention relates to an interface device between a network and an exchange and, more particularly, to an interface device for producing transmission clock timing information on user data (Transmission RTS information) in a broadband-ISDN (B-ISDN) by an SRTS (Synchronous Residual Time Stamp) method, transmitting the transmission RTS information together with the user data in the form of a cell, and conforming the timing of a reception clock with that of the transmission clock so as to output the user data in synchronism with the reception clock.
There is increasing demand not only for audio communication and data communication but also for multimedia communication in which moving pictures are transmitted as well as audio and data. B-ISDN (broadband-ISDN) switching technology, which is based upon an asynchronous transfer mode (ATM), has been agreed upon by the ITU-T as a means of realizing broadband communication for multimedia communication. Such technology is being put into practical use.
In an ATM system, logical links are multiplexed on a physical line so that a line may be allocated to a plurality of calls. Moving-picture data or audio data from a terminal corresponding to each call is broken down into fixed-length information units (referred to as"cells"), and the cells are transmitted over a line sequentially to realize multiplexing. As shown in FIG. 48, a cell is composed of a fixed-length block of 53 bytes of which five bytes constitute a header HD and 48 bytes an information field DT. In order that the destination will be understood even after data is broken down into blocks, the header HD includes a virtual channel identifier (VCI) for call identifying purposes. The header HD further includes a virtual path identifier (VPI) that identifies paths, a generic flow control (GFC) used in flow control between links, payload type (PT) and a head error control (HEC), which is a code for correcting errors in the header.
FIG. 49 is a diagram showing the configuration of an ATM network useful in describing an ATM system. Shown in FIG. 49 are terminals 1a, 1b and an ATM network 3. The ATM network 3 has an information network 3a that transmits data cells and a signal network 3b that transmits control signals. Call processing processors (CPU) 3d-1.about.3d-n of ATM exchanges 3c-1.about.3c-n in the information network 3a are connected to the signal network 3b.
When a call operation is performed so that the terminal 1a, which is on the originating side, may call the terminal 1b, which is on the terminating side, a cell assembler within the originating terminal 1a partitions data, which includes calling party number, called party number and the kind of the original terminal, as well as attributes, into cell units, attaches a signal VCI (determined in advance for each terminal) to each item of partitioned data to form a signal cell and sends the signal cells to the ATM network 3.
If a signaling device (not shown) of the ATM exchange (on the originating side) 3c-1 receives a signal cell, the signaling device assembles information contained in the signal cells and notifies the CPU 3d-1 of the information. The CPU executes such call processing as processing for analyzing the service registered to the calling-party, charging processing and processing for interpreting digits consisting of the called party number, decides a virtual path (VPI) and call identifying information (VCI) and, in accordance with a No. 7 protocol, sends to the next relay exchange 3c-2 connection information, such as the calling party number, called party number, VPI, VCI and other data, via the signal network 3b. The relay exchange 3c-2 executes processing similar to that of the originating exchange 3c-1. Thereafter, processing similar to that described is performed from exchange to exchange until finally a path from the originating exchange 3c-1 to the ATM exchange (the exchange on the terminating side) 3c-n, to which the terminating terminal is connected, is decided as well as the relay ATM exchanges 3c-2, 3c-3 . . . . If the terminating exchange 3c-n receives connection information containing the calling party number, the called party number and the VCI of the higher-order ATM exchange 3c-3 , then the exchange 3c-n assigns a prescribed VCI to the terminating terminal 1b and it is determined whether the terminating terminal 1b is capable of communicating. If communication is possible, then the signal network 3b notifies the originating exchage 3c-1 of the fact that communication is possible and the originating exchange assigns a prescribed VCI to the originating terminal 1a.
Each of the ATM exchanges 3c-1.about.3c-n on the paths registers the following, for each path, in an internal routing table in a form correlated with the VCI of the higher-order ATM exchange: (1) connection information (referred to as routing information or tag information for specifying the output path (outgoing highway) of the cell having the particular VCI, and (2) a new VCI and new VPI, which are added on to the output cell.
Thus, when a path is formed between the originating terminal 1a and the terminating terminal 1b, the two terminals send and receive call and answer cells and verify the communication procedure in mutual fashion. Thereafter, the originating terminal 1a breaks down data to be transmitted into prescribed byte lengths, adds on a header containing the allocated VCI to produce a cell and sends the cell to the ATM network 3. When each of the ATM exchanges 3c-1.about.3c-n is supplied with an input cell from the higher-order exchange via the prescribed incoming highway, the ATM exchange refers to its own routing table to replace the VPI/VCI of the input cell and sends the cell out on the prescribed outgoing highway based upon the tag information. As a result, the cell outputted by the originating terminal 1a arrives at the terminating exchange 3c-n via the path that has been decided by call control. The terminating terminal 3c-n refers to its routing table, changes the VCI attached to the inputted cell to the VCI allocated to the terminating terminal and then sends the cell to the line to which the terminating terminal 11b is connected.
Thereafter, the originating terminal 1a sends cells to the terminating terminal 1b in successive fashion and the terminating terminal 1b assembles the information field DT contained in the received cells, thereby restoring the original data.
The foregoing relates to a case for dealing with one call. However, by changing the mutually held VCI values at both ends of each line between the terminal and ATM exchange and between the mutually adjacent ATM exchanges, logical links conforming to a number of calls can be established on one line. As a result, high-speed multiplexed communication may be realized. In accordance with an ATM system, information from information sources such as moving pictures, data and audio having different transmission rates can be multiplexed. As a consequence, a single transmission line can be used in a very effective manner. Moreover, re-transmission control and complicated communication procedures such as those implemented by software through packet switching are no longer necessary and it is possible to achieve ultra-high-speed data transmission on the order of 150 Mbps.
FIGS. 50A to 50D show the structure of a broadband ISDN system. The ATM cells in these drawings are transmitted only from the right-hand side to the left-hand side, but actually ATM cells are transmitted in both directions. In FIG. 50A, ATM terminals 12, 13 are connected to an ATM exchange 11 and the communication between the ATM terminals 12 and 13 is conducted by the ATM cells through the ATM exchange 11. The symbol UNI represents a user network interface. In FIG. 50B, various user terminals 14, 15 are connected to the ATM terminals 12, 13. Each of the ATM terminals 12, 13 has a function of converting the data of a user terminal into an ATM cell and transmit it to the ATM exchange 11, and converting the ATM cell received from the ATM exchange 11 into the data for a user terminals and transmit it to the user terminal. In FIG. 50C, interworking function units (IWFU) 18, 19 are provided which have an interworking function with other networks (e.g., frame relay networks) 16, 17, and in FIG. 50D, an interface converting unit 11a is accommodated in the ATM exchange 11 so as to convert the data of another network to the ATM cell and vice versa in the ATM exchange 11.
In such a broadband ISDN system, there is a service of transmitting user data at a constant speed, i.e., a CBR (Constant Bit Rate) service. In this CBR service, it is necessary for the receiving apparatus to separate the user data from the received ATM cell and output the user data with the same timing (same frequency, same phase) as that of the transmission clock. For example, in the CBR service for transmitting sound at 64 kbps, it is necessary for the receiving apparatus to take out and output the received data at 64 kbps. If the frequency of the receiving apparatus is not more than 64 kbps, the output sound becomes slow and the buffer is full of the received data, so that some of the transmitted data are missed, which leads to a miss in sound. On the other hand, if the frequency of the receiving apparatus is not less than 64 kbps, the output sounds become rapid and the buffer assumes a vacant state, so that sound is output intermittently. Therefore, in the CBR service, it is necessary to conform the timing of the clock for receiving user data (hereinafter referred to as "data reception clock") with that of the clock for transmitting user data (hereinafter referred to as "data transmission clock", and both data reception clock and data transmission clock will be collectively referred to as "user clock").
If the data transmission clock is synchronous with the clock of the network, it is possible to conform the data transmission clock with the data reception clock by producing the data reception clock from the clock of the network by the receiving apparatus.
However, some data transmission clocks (e.g., 64 kbps of sound, 1.544 Mbps of DS1, 44.736 Mbps of DS3, etc. standardized by the ITU-DS (CCITT) Recommendation G700 series and the like), are not synchronous with the timing of the network clock. For example, in the structure shown in FIG. 50B, when the user terminals 14, 15 transmit user data by using their own clocks, or in the structure shown in FIG. 50C and D, when the network clock of each network is different from the network clock of the ATM network, the data transmission clocks are not synchronous with the timing of the network clock. In such a case, even if the nominal value of the frequency of the data transmission clock is known and the receiving apparatus produces the data reception clock having the same nominal value by dividing the clock (e.g., 155.52 MHz) of the network, there is a difference in timing between the data reception clock and the data transmission clock, so that faithful CBR service is impossible.
As a method of synchronizing a data reception clock with a data transmission clock, an SRTS (Synchronous Residual Time Stamp) method is proposed. In the SRTS method, the timing information on the data transmission clock is added to the ATM cell on the transmission side and the receiving side extracts the timing information on the data transmission clock and synchronizes the data reception clock with the data transmission clock on the basis of the timing information. In order to transmit the timing information on the data transmission clock, AAL-1 (ATM Adaptation Layer-1) standardized by ITU-DS Recommendation 1363 and the like is used as an ATM cell.
In this manner, the transmitted PCM data in DS1 and DS3 is converted into the ATM cell format of the AAL-1 (ATM Adaptation Layer-1) type and transmitted through an ATM switch.
FIG. 51 is an explanatory view of a format of an ATM cell of the AAL type (AAL-1), and FIG. 52 is an explanatory view of a format of an SAR-PDU header of 1 byte. The ATM cell of the AAL-1 (ATM Adaptation Layer-1) type has two sub-layers SAR (Segmentation AND Reassembly) and CS (Convergence). The SAR sub-layer has a function of indicating the order of data transmitting, and detecting and correcting an error, and the CS sub-layer has a function of transmitting and reproducing timing information.
In the AAL-1, an information field is composed of an SAR-PDU payload having a length of 47 bytes, and an SAR-PDU (Protocol Data Unit) header having a length of 1 byte. The SAR-PDU payload of 47 bytes is used for transferring user data, and the SAR-PDU header of 1 byte is composed of an SN (Sequence Number) field of 4 bits and an SNP (Sequence Number Protection) field of 4 bits.
The SN field is divided into two sub-fields (CSI (Convergence Sublayer Identifier) and SC (Sequence Count), and the SNP field is also divided into two sub-fields CRC (Cyclic Redundancy Check) and EPB (Even Parity Bit).
The SC sub-field is used for counting cells by recurring numbers 1 to 8 (1,2, . . . , 8, 1,2, . . . ,8, 1 , . . . ), and it is possible to monitor the order of cells by the SC. The CRC and EPB are used for detecting and correcting and error of the SN. The CRC is a value obtained from the polynomial (G(X) =X.sup.3 +X+1) with respect to the SN, and the EPB is an even parity bit of the SAR-PDU header. The CSI bit has a function of the CS of the AAL-1 and is used for transmission and reproduction of the timing information on a user clock, as will be described later.
In the SRTS method, the timing information on a user clock is composed of information on 4 bits (RTS4, RTS3, RTS2, RTS1) which is called RTS (Residual Time Stamp) information. The RTS information is transferred by the CSI bit, which has a function of the CS of the AAL-1. FIG. 53 is an explanatory view of the structure of the RTS information format. The RTS information format has a multi-frame structure corresponding to 8 ATM cells. Since user data is transferred in the SAR-PDU payload, the number of bits of the user data in the 8 ATM cells is 3008 bits (8 cells.times.47 bytes.times.8 bits).
The CSI bits are composed of 8 bits in correspondence with the values 0 to 7 of the SC (Sequence Count). The CSI bits (CS.sub.1, CS.sub.3, CS.sub.5, CS.sub.7) having SC values of 1, 3, 5 and 7 transfer the RTS information on 4 bits. That is, the information RTS4 is transferred by the ATM cell of the SC1, the RTS3 by the ATM cell of the SC3, the RTS2 by the ATM cell of the SC 5, and the RTS1 is transferred by the ATM cell of SC 7.
FIG. 54 is an explanatory view of the period of producing RTS information. In the CBR service, transmitted user data DTU is data transmitted at a constant speed, and the clock which is synchronous with the data is shown as the data transmission clock C.sub.TU in FIG. 54. In the ATM cell, the information on the transmitted user data DTU is transmitted in the SAR-PDU payload, and the RTS information, which is the timing information on the data transmission clock C.sub.TU is transmitted by the CSI bit. For this reason, if it is assumed that the frequency of the data transmission clock is f.sub.TU, and the time TTU for 1 bit of the user data is 1/f.sub.TU, the period T.sub.TS of producing RTS information is T.sub.TU .times.3008. If it is assumed that the clock for producing the RTS data is the RTS transmission sampling timing clock C.sub.TS, the RTS information is produced at the rise of the clock C.sub.TS. The RTS transmission sampling timing clock C.sub.TS corresponds to 1/3008 of the data transmission clock C.sub.TU.
In the SRTS method, the network clock frequency f.sub.N (e.g., 155.52 MHz) which is synchronous with the network timing is divided by X (X is an integer) so as to produce a frequency-divided network clock C.sub.NX (frequency f.sub.NX =f.sub.N /X). The value X is determined so that the ratio of the frequency-divided network clock f.sub.NX and the nominal value f.sub.NOM of the user clock frequency is in the range of 1.ltoreq.f.sub.NX /f.sub.NOM &lt;2 (N is an integer). X may be set at 2. In the following explanation, X is assumed to be 2.
The frequency-divided network clock is then divided by a 4-bit binary counter to produce network timing information Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 having frequencies of f.sub.NX /2.sup.1, f.sub.NX /2.sup.2, f.sub.NX /2.sup.3 and f.sub.NX /2.sup.4 respectively. The values obtained by sampling the network timing information Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 at the rise of the RTS transmission sampling timing clock C.sub.TS are the RTS information RTS4, RTS3, RTS2 and RTS1, respectively.
The production of the RTS information and the format for transmitting the same are regulated by the international recommendation as described above.
FIG. 55 shows the structure of RTS producing and transmitting portion for producing and transmitting RTS information in accordance with the international recommendation, and FIG. 56 shows the wave forms explaining the operation of the RTS producing and transmitting portion shown in FIG. 55.
An ATM cell decomposing portion 20 extracts the network clock C.sub.N (frequency f.sub.N : e.g., 155.52 MHz) contained in the ATM cell RATM received from the ATM network by a PLL (Phase Lock Loop) and outputs the extracted network clock C.sub.N. A network clock frequency dividing portion 21 divides the network clock C.sub.N which is synchronous with the network timing and outputs the frequency-divided network clock C.sub.NX. In this case, the network clock frequency dividing portion divides the network clock C.sub.N so that the ratio of the frequency f.sub.NX of the frequency-divided network clock and the nominal value f.sub.NOM of the frequency of the user clock is in the range of 1.ltoreq.f.sub.NX /f.sub.NOM &lt;2 (N is an integer). X may be set at 2. For example, since the nominal value of the frequency of the data reception clock is 1.544 MHz in DS1, if the frequency f.sub.N of the network clock is 155.52 MHz, N=6, and the frequency of the frequency-divided network clock is f.sub.NX =155.52 MHz/2.sup.6 =2.43 MHz.
A 4-bit binary counter portion 22 then counts the frequency-divided network clock C.sub.NX, and outputs the network timing information Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 having frequencies of f.sub.NX /2.sup.1, f.sub.NX /2.sup.2, f.sub.NX /2.sup.3 and f.sub.NX /2.sup.4, respectively, from each of four stages.
A transmission frequency division counter portion 23 divides the data transmission clock C.sub.TU (frequency f.sub.TU) which is synchronous with the transmitted user data D.sub.TU into 1/3008 so as to output the RTS transmission sampling timing clock C.sub.TS (frequency f.sub.TS =f.sub.TU /3008).
A transmission RTS information producing portion 24 samples the network timing information Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 at the rise of the RTS transmission sampling timing clock C.sub.TS and outputs the transmission RTS information TRTS1, TRTS2, TRTS3 and TRTS4. In the example shown in FIG. 56, since all of the Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 are 0 at a first rise of the RTS transmission sampling timing clock C.sub.TS, the value X.sub.H (H means hexa) of the transmission RTS information is 0. At a second rise of the RTS transmission sampling timing clock C.sub.TS, since the Q.sub.1, Q.sub.2, Q.sub.3, are 1 and Q.sub.4 is 0, the value X.sub.H of the transmission RTS information is 7. When the frequency f.sub.TU of the data transmission clock C.sub.TU changes, the rising time of the RTS transmission sampling timing clock C.sub.TS changes, so that the values X.sub.H of the transmission RTS information TRTS1 to TRTS4 also change. In other words, the transmission RTS information contains the timing information on the data transmission clock C.sub.TU.
An ATM cell assembling portion 25 assembles a multi-frame composed of eight ATM cells every 3008.times.T.sub.TU (see FIG. 56) by using the transmitted user data D.sub.TU, the data transmission clock C.sub.TU which is synchronous therewith and the transmission RTS information which is input from the transmission RTS information producing portion 24, and transmits the assembled ATM cells to the ATM network in synchronism with the network clock C.sub.N.
The value attached to each transmission ATM cell of the multiframe TATM shown in FIG. 56 is SC (Sequence Count), and the transmission RTS information TRTS1, TRTS2, TRTS3 and TRTS4 is added to the respective hatched cells.
In the international recommendation, only the production of RTS information and the format for transmitting the RTS information are regulated, and any technique of conforming the data reception clock with the data transmission clock is not recommended.
As a result, the following ATM interface devices are demanded:
(1) an ATM interface device for producing a data reception clock having the same timing (same frequency, same phase) with that of a data transmission clock by a receiving apparatus by using the RTS information transmitted from a transmitting apparatus; PA1 (2) an ATM interface device which is capable of reproducing a data reception clock up to 1/2 of a network clock frequency because the nominal value of a user clock has a wide range; PA1 (3) an ATM interface device which allows a receiving apparatus a wide frequency deviation because there is actually a deviation from the nominal value in a data transmission clock, and an ATM interface device in which there are few clock jitters because the reproduced clock is used as a data reception clock; PA1 (4) an ATM interface device which can reduce the power consumption and does not need a clock having a very high frequency because it does not require a high-speed element; PA1 (5) an ATM interface device which can shorten the time required for establishing the synchronization between a data transmission clock and a data reception clock and which has an improved synchronization stability; PA1 (6) an ATM interface device which can be subjected to an operation confirmation test and a confirmation test of the normality of an ATM switch; and PA1 (7) an ATM interface device which can establish synchronization between a data transmission clock and a data reception clock even if communication is exchanged through ATM networks having different network clocks.